In the circuit shown in Fig. 8A4, U5 pins 1 and 4 are high and both are in the reset state. Assume one clock cycle occurs of Clk A followed by one cycle of Clk B. What are the output states of the two D-type flip flops?
• Operation of a D-type flip-flop on the active clock edge (what happens to Q when the clock ticks) • Meaning of the reset (clear) state for the flip-flop outputs • The sequence of clocking: one cycle of Clk A first, then one cycle of Clk B, and how that affects each stage in turn
• Before any clocks, with both flip-flops in reset, what are pins 5 and 9? Now, after the first Clk A pulse, what happens to the first D flip-flop’s output based on its D input at that instant? • After the second clock (Clk B), how does the output of the first flip-flop influence the second flip-flop’s output? Track Q of the first device into the D input of the second at the moment Clk B is active. • Think carefully about whether either flip-flop changes state on the leading or trailing edge of the clock, and how that affects when data is actually transferred from D to Q.
• Verify what logical level reset forces on the Q outputs (pins 5 and 9) before any clocking. • Confirm from the figure which signal feeds the D input of each flip-flop, especially whether the second flip-flop’s D input comes from the first flip-flop’s Q. • Check the clock polarity (positive- or negative-edge triggered) in the figure so you know on which transition each flip-flop samples its D input.
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